Annealed wafer and method for manufacturing the same

ABSTRACT

The present invention provides an annealed wafer which has a wafer surface layer serving as a device fabricating region and having an excellent oxide film dielectric breakdown characteristic, and a wafer bulk layer in which oxide precipitates are present at a high density at the stage before the wafer is loaded into the device fabrication processes to give an excellent IG capability, and a method for manufacturing the annealed wafer. The present invention is directed to an annealed wafer obtained by performing heat treatment on a silicon wafer manufactured from a silicon single crystal grown by the Czochralski method, wherein a good chip yield of an oxide film dielectric breakdown characteristic in a region having at least a depth of up to 5 μm from a wafer surface is 95% or more, and a density of oxide precipitates detectable in the wafer bulk and each having a size not smaller than a size showing a gettering capability is not less than 1×10 9 /cm 3 .

This application is a 371 of PCT/JP03/12396 Sep. 9, 2003.

TECHNICAL FIELD

The present invention relates to an annealed wafer having a wafersurface layer with an excellent oxide film dielectric breakdowncharacteristic and a wafer bulk layer with an excellent getteringcapability, and a method for manufacturing the annealed wafer.

BACKGROUND ART

In recent years, with miniaturization of a device in consequence of anincrease in an integration level of a semiconductor circuit, there haverisen quality requirements for a silicon single crystal serving as asubstrate of the semiconductor circuit and grown by a Czochralski method(hereinafter referred to, for brevity, as the “CZ method”). Inparticular, there exist defects due to single crystal growth calledgrown-in defects such as FPD, LSTD, and COP, which deteriorate an oxidefilm dielectric breakdown characteristic and the characteristics of adevice. A decrease in the density and sizes of the defects is regardedas important.

In explanation of these defects, first there will be described belowgenerally known matters for factors to determine a taken inconcentration each of a void type point defect called vacancy(hereinafter may be also briefly referred to as V), and an interstitialsilicon point defect called interstitial-Si (hereinafter may be alsobriefly referred to as I) both taken in a silicon single crystal.

In a silicon single crystal, a V region is a vacancy, i.e., a regionrich in recessed portions, holes and the like formed due to shortage ofsilicon atoms, and an I region is a region rich in dislocations andblocks of silicon atoms generated by the presence of excessive siliconatoms. As a result, a neutral (hereinafter may be also briefly referredto as N) region in which atoms are not short or excessive (or rarelyshort or excessive) is present between the V region and the I region. Ithas been come out that grown-in defects (FPD, LSTD, COP, and the like)absolutely generate when the V or I is oversaturated, and when the V orI is not saturated, even though the distribution of atoms may beslightly biased, the above defects are not present.

The densities of both the point defects are determined depending on therelationship between a pulling rate (growth rate) of a crystal in the CZmethod and a temperature gradient G in the neighborhood of asolid-liquid interface in the crystal. It is confirmed that in theneighborhood of the boundary between the V region and the I region,defects called an OSF (Oxidation Induced Stacking Fault) are distributedin the form of a ring (hereinafter may be also referred to as an OSFring) when seeing them as a cross section in a direction perpendicularto the crystal grow axis.

These defects due to crystal growth are exhibited as a defectdistribution map as shown in FIG. 9 when there is changed from high tolow a growth rate of a crystal along a crystal axis by a CZ pullingmachine using an in-furnace structure (hot zone: may be also referred toas an HZ) having a temperature gradient in the neighborhood of a usualsolid-liquid interface in the crystal.

These defects caused by crystal growth are classified as follows. Whenthe growth rate is relatively high, e.g., about 0.6 mm/min or more,there exist grown-in defects such as FPD, LSTD, and COP due to voidswhere void-type point defects collect together at a high density in anentire area in a direction of crystal diameter. The region in whichthese defects exist is called a V region (line (A) in FIG. 9).

When the growth rate is below 0.6 mm/min, with a decrease in growthrate, an OSF ring generates in the periphery of the crystal, and defectsof L/D (Large Dislocation: an abbreviation of an interstitialdislocation loop, LSEPD, LFPD or others) which are considered to be dueto a dislocation loop exist outside the ring at a low density. Theregion where these defects exist is called an I region (may be alsoreferred to as an L/D region). In addition, when the growth rate islowered to about 0.4 mm/min or less, the OSF ring aggregates and becomesextinct about the center of the wafer, thereby the entire region turninginto the I region (line (C) in FIG. 9).

In recent years, the presence of a region, called an N region, whichdoes not include FPD, LSTD, and COP due to the voids, and LSEPD and LFPDdue to the dislocation loop is detected outside the OSF ring between theV region and the I region. It is reported that the N region existsoutside the OSF ring, and when the N region is subjected to an oxygenprecipitation heat treatment and then the contrast of the precipitationis checked by X-ray observation or the like, oxygen is rarelyprecipitated therein and the N region is on the I region side which isnot so rich that LSEPD and LFPD are formed.

Since the N region exists diagonally to the growth axis direction in ausual method when a growth rate is decreased, the N region exists partlyon a wafer surface (line (B) in FIG. 9). As to the N region, theVoronkov theory (V. V. Voronkov; Journal of Crystal Growth, 59 (1982)625 to 643) advocates that a parameter, i.e., F/G that is a ratio of apulling rate (F) to a temperature gradient (G) in an axial direction ofa crystal solid-liquid interface determines a total concentration ofpoint defects. Depending on the theory, since the pulling rate should beconstant on the wafer surface, due to a distribution of the temperaturegradient (G) on the wafer surface, for example, there could be onlyobtained a crystal in which the N region is sandwiched between the Vregion at the center and the I region at the periphery.

Recently, by improving the distribution of the temperature gradient (G)on the wafer surface, for example, when the crystal is pulled whilegradually decreasing the pulling rate (F), there can be produced acrystal where the N region which exists only diagonally in a prior artspreads on a lateral entire surface at a certain pulling rate. In orderto longitudinally enlarge the crystal where the N region spreads on alateral entire surface, it is enough to some extent to pull the crystalwhile keeping a pulling rate at which the N region laterally spreads. Inaddition, considering the fact that the temperature gradient (G) changesin company with the growth of crystal, the change of the temperaturegradient (G) is compensated, and the pulling rate is controlled suchthat the F/G is constant; therefore the crystal portion where the Nregion entirely spreads can also be enlarged in the growing direction(for example, JP A 8-330316).

The N region is further classified into an Nv region (a region rich inthe voids) adjacent to the outside of the OSF ring and an Ni region (aregion rich in the interstitial silicon) adjacent to the I region. Itbecame clear that when performing thermal oxidation treatment, in the Nvregion, there is generated a large amount of oxide precipitates and inthe Ni region, there are rarely generated oxide precipitates (forexample, JP A 2001-139396).

However, it has become clear that a very large number of oxide filmdefects may be generated even in a single crystal where an N regionspreads on the entire surface, an OSF ring is not generated whenperforming thermal oxidation treatment, and FPD and L/D are not presenton the entire surface. This is a cause of deteriorating electriccharacteristics such as an oxide film dielectric breakdowncharacteristic. In order to realize excellent electric characteristics,there is not satisfied the conventional single crystal where the Nregion spreads on the entire surface, and further improvements aredesired.

Some of the present inventors have more exactly examined an N region bya Cu deposition method and have found that there exists a region Dn inwhich defects detected by the Cu deposition method drastically aregenerated, and which exists in the N region outside the OSF region andin a part of an Nv region where oxide precipitates easily generate afterperforming precipitation heat treatment (FIG. 10). The inventors havelocated the fact that the Dn region is a cause of deteriorating electriccharacteristics such as an oxide film dielectric breakdowncharacteristic, which already has been taught (JP A 2002-201093).

Therefore, if there can be spread on the entire wafer surface a regionwhich is the N region outside the OSF region and is free from a defectregion Dn detected by the Cu deposition method, there can be obtained awafer which is free from the various grown-in defects and can reliablyimprove an oxide film dielectric breakdown characteristic or the like.

The Cu deposition method is a wafer evaluation method that canaccurately measure the positions of defects of a semiconductor wafer,can improve detection limit to the defects of the semiconductor wafer,and can accurately measure and analyze more microscopic defects.

In a concrete wafer evaluation method, an insulating film having apredetermined thickness is formed on a wafer surface, and the insulatingfilm on a defective portion formed in the vicinity of the surface of thewafer is broken to deposit an electrolyte such as Cu at the defectiveportion. More specifically, the Cu deposition method is an evaluationmethod using the fact that when a potential is applied to an oxide filmformed on the wafer surface in a liquid in which Cu ions are dissolved,a current flows in a portion where the oxide film is deteriorated, andthe Cu ions are deposited as Cu. It is known that defects such as COPare present at a portion where the oxide film is easily deteriorated.

The defective portion of the wafer on which Cu is deposited are analyzedunder a focused light or directly visually analyzed to evaluate thedistribution and the density thereof. In addition, the defectivepositions can also be checked with a microscopic observation such as atransmission electron microscope (TEM) or a scanning electron microscope(SEM).

The terms will be explained below.

-   1) FPD (Flow Pattern Defect): A wafer is sliced from a grown silicon    single crystal rod, a surface distorted layer is removed by etching    using a liquid mixture of a hydrofluoric acid and a nitric acid, and    the surface is etched (Secco etching) by a liquid mixture of    K₂Cr₂O₇, a hydrofluoric acid and water to form pits and a ripple    pattern (a flow pattern). The flow pattern is called an FPD, and the    higher the FPD density on the wafer surface, the more the poor oxide    film dielectric breakdown characteristic (see JP A 4-192345).-   2) SEPD (Secco Etch Pit Defect): When performing the Secco etching    described above in the FPD, a defect which is accompanied by a flow    pattern is called an FPD, and a defect which is not accompanied by a    flow pattern is called an SEPD. It is conceivable that an SEPD    (LSEPD) having 10 μm or more is due to a dislocation cluster;    therefore when a device includes a dislocation cluster, current    leaks through the dislocation, and the device does not function as a    P-N junction.-   3) LSTD (Laser Scattering Tomography Defect): A wafer is sliced from    a grown silicon single crystal rod, a surface distorted layer is    removed by etching using a liquid mixture of a hydrofluoric acid and    a nitric acid, and then the wafer is cleaved. Infrared rays are    incident on the cleaved surface (or the wafer surface) to detect    rays emitted from the wafer surface (or the cleaved surface), so    that scattered light caused by defects present in the wafer can be    detected. This defect is called a LSTD. A scattering object observed    here has been reported at an academic society or the like, and is    regarded as an oxide precipitate (see Japanese Journal of Applied    Physics Vol. 32, p. 3679, 1993). In addition, a recent study has    reported that the scattering object is an octahedral void (hole).-   4) COP (Crystal Originated Particle): This defect causes    deterioration of the oxide film dielectric breakdown characteristic    of the central portion of a wafer. The defect which is an FPD in the    Secco etching is a COP in the SC-1 cleaning (cleaning by a liquid    mixture of NH₄OH: H₂O₂: H₂O=1:1:10) because the liquid mixture    serves as a selective etchant. The diameter of the pit is 1 μm or    less, and is checked by a light scattering method.-   5) L/D (large Dislocation: an abbreviation of an interstitial    dislocation loop): This defect includes an LSEPD, an LFPD, and the    like, and is a defect which is considered to be due to a dislocation    loop. An LSEPD is an SEPD having 10 μm or more as described above.    An LFPD is an FPD having a distal-end pit having a size of 10 μm or    more, and is also considered to be due to a dislocation loop.

On the other hand, a silicon single crystal grown by the Czochralskimethod includes interstitial oxygen at a concentration of 10¹⁸ atoms/cm³as an impurity. The interstitial oxygen is precipitated by asupersaturation in a thermal history from solidification to cooling to aroom temperature in the crystal growth step (hereinafter may be brieflyreferred to as a crystal thermal history) or in the heat treatment inthe fabricating step for a semiconductor device, so that a precipitateof a silicon oxide (hereinafter may be also referred to as an oxideprecipitate or simply a precipitate) is formed.

The oxide precipitate effectively serves as a site that captures a heavymetal impurity contaminated in device fabrication processes (InternalGetting: IG) to improve device characteristics or a yield. For thisreason, as one of qualities of a silicon wafer, the IG capability isregarded as important.

The process of oxygen precipitation includes the formation ofprecipitation nuclei and the growth process thereof. In a usual as-growwafer, the nucleus formation progresses in the crystal thermal history,and the nuclei are largely grown by heat treatment in the devicefabrication processes and other processes performed thereafter, thegrown nuclei being detectable as oxide precipitates. Therefore, theoxide precipitates which are present before loading the wafer into thedevice fabrication processes are extremely small, and do not have the IGcapability. However, by loading the wafer into the device fabricationprocesses, the oxide precipitates are grown to large ones to have the IGcapability.

On the other hand, in recent device fabrication processes, with anincrease in diameter of a wafer to be used, there progresses lowering intemperature and shortening in processing time. For example, a series ofdevice fabrication processes are performed at a temperature of 1000° C.or less, or RTP (Rapid Thermal Processing) that requires only a heattreatment time of about several ten seconds has been frequently used.Since all the heat treatment performed in the device fabricationprocesses may totally correspond to only the heat treatment performed at1000° C. for about 2 hours, unlike the prior art, growth of oxideprecipitates in the device fabrication processes cannot be expected. Forthis reason, in the device fabrication processes where low temperatureand short processing time are realized, it is necessary for the wafer tohave the excellent IG capability before loading it into the devicefabrication processes. More specifically, large oxide precipitatesdetectable before loading the wafer into the device fabricationprocesses are desirably formed at a high density.

On the other hand, the presence of oxide precipitates in a devicefabricating region in the vicinity of the wafer surface deterioratesdevice characteristics. For this reason, it is desirable that oxideprecipitates are not present in the vicinity of the wafer surface.

In a general CZ wafer, as so-called grown-in defects generated by athermal history when pulling crystal, in addition to grown-in oxygenprecipitation nuclei, there exist voids defects formed by aggregation ofvacancies. When the voids are exposed on the surface of amirror-polished wafer, the voids turn into surface pits called COP. Thepresence of COP and voids in the device fabricating region deterioratesdevice characteristics. In particular, it is known that the COP andvoids deteriorate an oxide film dielectric breakdown characteristic thatis an important characteristic. From the above fact, it is desirablethat not only the oxide precipitates but also the COP and voids are notpresent in the device fabricating region (usually at a depth of aboutseveral μm from the surface) of the wafer surface layer.

In order to annihilate the COP and voids in the wafer surface layer,high-temperature heat treatment at about 1200° C. may be performed in ahydrogen atmosphere or an inert gas atmosphere such as an argonatmosphere. In this case, it is preferable that the IG capability isgiven. For this reason, as a method for simultaneously realizingelimination of the COP and voids in the vicinity of the wafer surfaceand formation of oxide precipitates in the wafer bulk, methods foradding nitrogen when growing a crystal are proposed (for example, JP A11-322490, 11-322491, and 2000-211995, and the like).

In the wafer added with nitrogen, voids can be easily eliminated by thehigh-temperature heat treatment in the vicinity of the wafer surfacebecause the voids decrease in size, and since grown-in precipitationnuclei formed by a crystal thermal history increase in size, theprecipitation nuclei are grown without being eliminated even in thehigh-temperature heat treatment in the wafer bulk to form oxideprecipitates, with the result that the IG capability is given.

However, even when the wafer having nitrogen added thereto is used,high-temperature heat treatment at about 1200° is required to eliminatethe voids in the surface layer; in some cases, small size voids whichbelong to the size level not detectable may be left. In addition, sincelarge grown-in precipitation nuclei are thermally stable, they are noteasily eliminated even in the wafer surface layer and may be left in thesurface layer. When these defects are left in the surface layer, thereoccurs a problem that device characteristics are deteriorated.

In addition, when nitrogen is added when growing a crystal, the crystalproducing steps are complicated, and control of a nitrogen concentrationrequires much labor.

DISCLOSURE OF THE INVENTION

With the foregoing problem of the prior art in view, it is an object ofthe present invention to provide an annealed wafer which has anexcellent oxide film dielectric breakdown characteristic in a wafersurface layer serving as a device fabricating region, oxide precipitatespresent in a wafer bulk layer at a high density before loading the waferinto device fabrication processes, and an excellent IG capability, and amethod for manufacturing the annealed wafer.

In order to solve the above problem, an annealed wafer according to thepresent invention is obtained by performing heat treatment on a siliconwafer manufactured from a silicon single crystal grown by theCzochralski method, wherein a good chip yield of an oxide filmdielectric breakdown characteristic in a region having at least a depthof up to 5 μm from a wafer surface is 95% or more, and a density ofoxide precipitates detectable in the wafer bulk and each having a sizenot smaller than a size showing a gettering capability is not less than1×10⁹/cm³.

Here, the oxide film dielectric breakdown characteristic in the presentinvention is a TZDB (Time Zero Dielectric Breakdown) characteristic. Thegood chip yield is a ratio of the chips each having a dielectricbreakdown electric field of 8 MV/cm or more at a decision current of 1mA/cm².

As described above, since a denuded zone having an excellent oxide filmdielectric breakdown characteristic is formed in not only the wafersurface but also a deep region of at least a depth of up to 5 μm fromthe wafer surface, even in a device using the deep region, thecharacteristics thereof are not deteriorated.

As a simple method for detecting defects in the wafer surface layer, aparticle counter or a selective etching method is known. However, evenwhen the defects are not detected by these methods, the presence ofdefects each having a small size that is not larger than a detectionlimit may deteriorate the oxide film dielectric breakdowncharacteristic. For this reason, it is very important for the wafer tohave an excellent oxide film dielectric breakdown characteristic.Needless to say, it is preferable that a good chip yield is 100%.

At the stage before loading the wafer into the device fabricationprocesses, when a density of oxide precipitates detectable in the waferbulk except for the denuded zone is 1×10⁹/cm³ or more, even in therecent device fabrication processes where the low temperature and shortprocess time are realized, the oxide precipitate serves as a getteringsite from the initial stage of the device fabrication processes, and asufficient gettering capability can be achieved. In consideration of themechanical strength of the wafer, the density of oxide precipitates ispreferably set to 1×10¹³/cm³ or less.

In this case, the experimentally detectable size of the oxideprecipitate (about 30 to 40 nm in diameter) serves as a measure of thesize of an oxide precipitate having an IG capability. It is generallyconsidered that oxide precipitates each having the experimentallyundetectable size have an IG capability; the experimentally detectablesize thereof may conceivably achieve a sufficient IG capability.Therefore, as the size having a gettering capability, a diameter ofabout 40 nm or more is preferably used. Such oxide precipitates aredetectable by an infrared scattering tomography which is one of lightscattering methods.

Furthermore, a silicon wafer subjected to heat treatment as a startingwafer of the annealed wafer according to the present invention ispreferably a silicon wafer which is manufactured from a silicon singlecrystal grown under a condition that, when growing the silicon singlecrystal, a wafer entire surface is an N region which is formed outsidean OSF generated in the form of a ring in a thermal oxidation process,and is free from a defective region detectable by a Cu depositionmethod.

In the Cu deposition method, COP and voids are detectable with highsensitivity. Therefore, it may be determined that voids are not presentin a wafer which is free from a detective region detected by the Cudeposition method. In an annealed wafer obtained by heat treating asilicon wafer having no defective region detectable by the Cu depositionmethod, defects detectable by the Cu deposition method are not presentand annealing is added, so that the oxide film dielectric breakdowncharacteristic of the wafer surface layer are more excellent.

As a silicon wafer to be subjected to heat treatment as a starting waferof the annealed wafer according to the present invention, there ispreferably used a wafer manufactured from a silicon single crystal grownwithout adding nitrogen when growing the silicon single crystal.

By adding no nitrogen, thermally stable large grown-in precipitationnuclei (for example, 40 nm or more in diameter) are not present, withthe result that there is no risk of the grown-in precipitation nucleibeing left in the surface layer after the heat treatment (annealing). Inaddition, no necessity of adding nitrogen leads to the advantages thatthe crystal growing step is not complicated and management or the likebecomes easy.

Further, as a silicon wafer to be subjected to heat treatment as astarting wafer of the annealed wafer according to the present invention,there may be used a less defective wafer having almost no COP and voidswhich is manufactured from a silicon single crystal pulled under acondition that, when growing the silicon single crystal, void defectsare suppressed.

The less defective wafer, as described in JP A 11-147786, JP A 11-157996and the like, is a silicon wafer having the entire surface of N regionwhich can be obtained by using a known technique for pulling a crystalwhile controlling a ratio F/G of a crystal pulling rate F and atemperature gradient G in the vicinity of a solid-liquid interface inthe crystal.

A first aspect of the method for manufacturing an annealed waferaccording to the present invention comprises the steps of: manufacturinga silicon wafer from a silicon single crystal obtained by growing thesilicon single crystal under controlling a growth rate between a firstgrowth rate at a boundary where a defective region left afterannihilation of an OSF ring and detectable by a Cu deposition method isannihilated when the growth rate of pulling a silicon single crystal isgradually reduced, and a second growth rate at a boundary where aninterstitial dislocation loop is generated when the growth rate isfurther gradually reduced in case of growing the silicon single crystalby a Czochralski method; keeping the silicon wafer having grown-inprecipitation nuclei formed in the step of growing the silicon singlecrystal at a temperature of T₄° C. in the range of 500° C. to 700° C.for a predetermined time t₁; increasing the temperature of the siliconwafer to a temperature of T₅° C. in the range of 1000° C. to 1230° C.with a temperature increase rate of 5° C./min or less; and keeping thesilicon wafer at the temperature of T₅° C. for a predetermined time t₂,whereby the grown-in precipitation nuclei are grown to oxideprecipitates each having a size not smaller than a size having agettering capability and oxygen in the vicinity of the silicon wafersurface is outdiffused.

Thus, the temperature of the silicon wafer is slowly increased from alow temperature (T₄° C.) to a high temperature (T₅° C.) with atemperature increase rate of 5° C./min or less and then the siliconwafer is kept at a high temperature for the predetermined time, wherebythe grown-in precipitation nuclei in the wafer bulk are not annihilatedand can be efficiently grown to oxide precipitates each having a sizenot smaller than a size having a gettering capability. At the same time,by outdiffusing oxygen in the vicinity of the wafer surface, the oxygenprecipitation nuclei can be eliminated, so that a DZ layer free of oxideprecipitates is formed in the vicinity of the wafer surface. Inaddition, the DZ layer becomes a high quality one in which defectsdetectable by the Cu deposition method are not present. That is,according to the first aspect of the method for manufacturing anannealed wafer of the present invention, a very high quality DZ-IGstructure can be formed by only simple one step heat treatment.

Here, as described above, the experimentally detectable size of theoxide precipitate (about 30 to 40 nm in diameter) serves as a measure ofthe size of an oxide precipitate having an IG capability. Therefore, thesize having a gettering capability is preferably set to about 40 nm ormore in diameter. In addition, although the upper limit of the size ofthe oxide precipitate is not specified, a long heat treatment time isrequired to largely grow the precipitates, so the diameter is preferablyset to 100 nm or less.

When the temperature of T₅° C. is lower than about 1000° C., a timerequired to grow a large oxide precipitate becomes long, and a wholeprocess time also becomes long. The higher the temperature of T₅° C.,the shorter the time required to grow a large oxide precipitate, andhence the total process time can be shortened. However, at a hightemperature exceeding about 1230° C., metal contamination from a heattreatment furnace becomes conspicuous; therefore, the temperature ispreferably set to 1230° C. or lower.

The lower the temperature of T₄° C., the higher the precipitate density.However, since the process time becomes long, the temperature of T₄° C.is preferably set to about 500° C. or higher. When the temperatureexceeds about 700° C., there are some cases where a sufficientprecipitate density may not be obtained. Similarly, the lower thetemperature increase rate R° C./min, the higher the precipitate density.However, when the temperature increase rate is too low, the process timeis long; the temperature increase rate is preferably set to about 1°C./min or more. When the temperature increase rate R° C./min becomes ahigh rate exceeding about 5° C./min, grown-in precipitation nucleicannot grow and may be annihilated at a high rate, and there are somecases where the sufficient precipitate density may not be obtained.

By setting the temperature increase rate R° C./min from the temperatureof T₄° C. to the temperature of T₅° C. to 5° C./min or lower, grown-inprecipitation nuclei are not annihilated to the utmost and can beefficiently grown. More specifically, since existing grown-inprecipitation nuclei formed in the crystal growing step is grown, theprecipitate density can be made sufficiently high without the heattreatment step for forming new oxygen precipitation nuclei, and moreoverthe total process time can be shortened.

In the first aspect of the method for manufacturing an annealed waferaccording to the present invention, before the temperature is increasedfrom the temperature of T₄° C. to the temperature of T₅° C., the keepingtime t₁ at the temperature of T₄° C. may be zero minute, but ispreferably set to 15 minutes or more. In this manner, the grown-inprecipitation nuclei are more difficult to annihilate, and furthermore,in addition to the grown-in precipitation nuclei, new oxygenprecipitation nuclei can be generated, whereby oxygen precipitationnuclei having a higher density can be formed. When the keeping time t₁is elongated, the process time becomes long. For this reason, thekeeping time t₁ is preferably set to about 60 minutes or shorter.

Incidentally, the lower the temperature of T₄° C. or the longer thekeeping time t₁ at the temperature of T₄° C. or the lower thetemperature increase rate, the higher the precipitate density becausenew precipitation nuclei are formed in the temperature increase step.

A keeping time t₂ at the temperature of T₅° C. is preferably set toabout 30 minutes or more to reliably grow the grown-in precipitationnucleus to a size having a gettering capability or to form the DZ layerhaving a sufficient width. The longer the holding time t₂, the largerthe sizes of the oxide precipitate in the wafer bulk, and hence the DZwidth in the vicinity of the wafer surface can be increased. However,since the process time becomes long, the keeping time t₂ is preferablyset to about 4 hours or shorter, and more preferably about 2 hours orshorter. On the other hand, when the keeping time t₂ is shorter thanabout 30 minutes, there arises a possibility that an oxide precipitatehaving a desired size or a desired DZ width may not be obtained due to aslight variation in time.

In order to sufficiently obtain the effect of the first aspect of themethod for manufacturing an annealed wafer according to the presentinvention, an oxygen concentration of a silicon wafer to be subjected toheat treatment is desirably set to about 14 ppma or higher. When theoxygen concentration is high, the precipitate density becomes high andan excellent IG capability can be achieved. In addition, the higher theoxygen concentration, the higher the growth rate of the precipitates,with the result that a total process time becomes short. Incidentally,even though the oxygen concentration is low, for example, thetemperature increase start temperature T₄° C. in the temperatureincrease step is lowered, or the keeping time at the temperature of T₅°C. is elongated, whereby the effect of the first aspect of the methodfor manufacturing an annealed wafer according to the present inventioncan be obtained. Therefore, in the first aspect of the method formanufacturing an annealed wafer according to the present invention, theupper limit of the oxygen concentration is not specified. However, inconsideration of the easiness of producing a silicon single crystal, theoxygen concentration is preferably set to about 23 ppma or less. Apreferable oxygen concentration is in the range of 14 to 17 ppma.

According to the first aspect of the method for manufacturing anannealed wafer of the present invention, there is obtained an effect ofsuppressing slip dislocation from being generated by thermal stress indevice fabrication processes. It is known that the dislocationconstituting the slip is subjected to pinning by an oxide precipitate.Therefore, when oxide precipitates each having a large size to someextent are formed at a high density by the first aspect of the methodfor manufacturing an annealed wafer of the present invention, thedislocation is subjected to pinning at a high probability, with theresult that the generation of the slip dislocation is suppressed. Thatis, the first aspect of the method for manufacturing an annealed waferof the present invention can be preferably used for a large diameterwafer having a diameter of 300 mm or larger where the slip dislocationis easily generated by heat treatment. In order to suppress thegeneration of the slip dislocation, the temperature of T₅° C. ispreferably set to 1200° C. or lower, and more preferably set to about1150° C. or lower.

In addition, according to the first aspect of the method formanufacturing an annealed wafer of the present invention, there can beformed a wafer of a very high quality DZ-IG structure where not onlyoxide precipitates but also COP and voids are rarely present withoutperforming high-temperature heat treatment at about 1200° C. This methodis especially effectively applied to a 300 mm wafer that will be amainstream in the future from the viewpoint of suppressing thegeneration of the slip.

A second aspect of the method for manufacturing an annealed wafer of thepresent invention comprises the steps of: manufacturing a silicon waferfrom a silicon single crystal obtained by growing the silicon singlecrystal under controlling a growth rate between a first growth rate at aboundary where a defective region left after annihilation of an OSF ringand detectable by a Cu deposition method is annihilated when the growthrate of pulling a silicon single crystal is gradually reduced, and asecond growth rate at a boundary where an interstitial dislocation loopis generated when the growth rate is further gradually reduced in caseof growing the silicon single crystal by a Czochralski method; and heattreating the silicon wafer having grown-in precipitation nuclei formedin the step of growing the silicon single crystal to give a gettingcapability to the silicon wafer, wherein there are performed at leastthree steps including a temperature increase step A₁ for growing thegrown-in precipitation nuclei, a temperature increase step B₁ forincreasing a temperature to a higher keeping temperature, and aconstant-temperature keeping step C₁ for growing the grown-inprecipitation nuclei to oxide precipitates each having a size notsmaller than a size having a gettering capability and for outdiffusingoxygen in the vicinity of the silicon wafer surface. It is desirablethat the temperature increase step A₁, the temperature increase step B₁,and the constant-temperature keeping step C₁ are continuously performedin the order of the steps.

In the second aspect of the method for manufacturing an annealed waferaccording to the present invention, the temperature increase step A₁ isthe step of increasing a temperature from T₆° C. to T₇° C. at a rate ofR₃° C./min. It is preferable that T₆° C. is 700° C. or lower, T₇° C. is800° C. to 1000° C., and R₃° C./min is 3° C./min or lower.

The lower the temperature of T₆° C., the higher the density of thegrowable grow-in precipitation nuclei. However, since there becomes longthe process time required to grow the grow-in precipitation nuclei, thetemperature of T₆° C. is preferably set to about 500° C. or higher. Whenthe temperature exceeds about 700° C., there are some cases where asufficient precipitate density may not be obtained.

When the temperature of T₇° C. is lower than 800° C., grown-inprecipitation nuclei are not sufficiently grown in the temperatureincrease step A₁, and are annihilated at a high rate in the subsequenttemperature increase step B₁, with the result that there are some caseswhere a sufficient precipitate density may not be obtained. When thetemperature of T₇° C. exceeds 1000° C., grown-in precipitation nuclei inthe vicinity of the wafer surface are largely grown, and after thesubsequent temperature increase step B₁ and the subsequent constanttemperature keeping step C₁, they are still left in the vicinity of thewafer surface, with the result that the precipitate density in the DZlayer may increase.

The lower the rate of R₃° C./min, the higher the precipitate densitybecause there increases a rate of grown-in precipitation nuclei grownwithout being annihilated. For this reason, in order to obtain asufficient precipitate density, the rate of R₃° C./min is preferably setto 3° C./min or lower. However, when the rate is too low, the processtime is elongated to spoil efficiency; the rate of R₃° C./min ispreferably set to 0.5° C./min or higher.

By performing the temperature increase step A₁, grown-in precipitationnuclei can be efficiently grown without being annihilated to the utmost.More specifically, since existing grown-in precipitation nuclei formedin the crystal growth step are grown, the precipitate density can bemade sufficiently high without using a heat treatment step for formingnew oxygen precipitation nuclei. In addition, a total process time canbe shortened.

Before the temperature is increased from T₆° C. to T₇° C. in thetemperature increase step A₁, a keeping time t₃ at the temperature ofT₆° C. may be 0 minute, but is preferably set to 30 minutes or longer.By adopting this manner, the grown-in precipitation nuclei areannihilated with more difficulty, and not only the grown-inprecipitation nuclei but also new oxygen precipitation nuclei can begenerated; the oxygen precipitation nuclei can be formed at a higherdensity. When the keeping time T₃ is elongated, a process time becomeslong, so that the holding time is preferably set to about 4 hours orshorter.

The temperature increase step B₁ is the step of increasing thetemperature from T₇° C. to T₈C at a rate of R₄° C./min. It is preferablethat T₇° C. is 800° C. to 1000° C., T₈° C. is 1050° C. to 1230° C., andR₄° C./min is 5° C./min or higher. In the temperature increase step B₁,by increasing the temperature to a high temperature in a short time,oxide precipitates in the vicinity of the wafer surface can besuppressed from being grown to make it easy to annihilate the oxideprecipitates in the vicinity of the wafer surface in the subsequentconstant-temperature keeping step C₁.

By setting the temperature of T₈° C. to 1050° C. or higher, oxideprecipitates in the wafer bulk can be efficiently grown to have asufficient size, and by outdiffusing oxygen in the vicinity of the wafersurface, the oxide precipitates in the vicinity of the wafer surface canbe annihilated. The higher the temperature of T₈° C., the larger theprecipitates in the wafer bulk besides the wider the DZ width. However,when the temperature of T₈° C. is a high temperature exceeding about1230° C., metal contamination from a heat treatment furnace becomesconspicuous; therefore the temperature of T₈° C. is preferably set to1230° C. or lower.

When the rate of R₄° C. is lower than 5° C./min, the oxide precipitatesin the vicinity of the wafer surface are largely grown to make itdifficult to annihilate the oxide precipitates in the subsequentconstant-temperature keeping step C₁. However, when the rate of R₄° C.is excessively high, the oxide precipitates in the wafer bulk areannihilated at a high rate, and the precipitate density is lowered;therefore, the rate of R₄° C. is desirably set to 10° C./min or lower.

The constant-temperature keeping step C₁ is the step of keeping atemperature of T₈° C. for a time t₄. It is preferable that thetemperature of T₈° C. is in the range of 1050° C. to 1230° C. and thatthe time t₄ is 30 minutes or longer. The constant-temperature keepingstep C₁ can make microscopic oxide precipitates grown in the precedingtemperature increase steps A₁ and B₁ grown to large oxide precipitateshaving IG capabilities in the wafer bulk, and annihilated in thevicinity of the wafer surface. Since the starting wafer does not includedefects detected by the Cu deposition method, the wafer subjected toheat treatment does not include defects as a matter of course.Therefore, there can be formed a wafer with a high-quality DZ-IGstructure serving as a defect free DZ layer and an IG layer having anexcellent IG capability.

The longer the keeping time t₄ at the temperature of T₈° C., the largerthe sizes of oxide precipitates in the wafer bulk layer besides thewider the DZ width. However, since the process time becomes long, thekeeping time t₄ is set to about 4 hours or shorter. On the other hand,when the keeping time t₄ is shorter than about 30 minutes, there may notbe obtained oxide precipitates each having a desired size and a desiredDZ width due to a small variation in time.

In addition, by changing the keeping temperature of T₈° C. and thekeeping time t₄, the size of the oxide precipitate and the DZ width canbe easily changed. It is considered that the larger the size of theoxide precipitate, the higher the IG capability. However, the largersize oxide precipitate needs the longer process time. Therefore, inorder to efficiently obtain oxide precipitates having a required sizeand a required DZ width, it is important that there is present an effectof making it possible to easily change the size of the oxide precipitateand the DZ width.

Wafers can be unloaded from the furnace during a period between thetemperature increase step A₁ and the temperature increase step B₁ andduring a period between the temperature increase step B₁ and theconstant-temperature keeping step C₁. However, the three steps arecontinuously performed, whereby the total process time can be moreshortened.

After the constant-temperature keeping step C₁, when unloading a waferfrom a heat treatment furnace, an inside temperature of the heattreatment furnace and a temperature decrease rate to the insidetemperature are not specified. However, the inside temperature and thetemperature decrease rate are desirably determined such that a slip dueto thermal stress may not be generated. For example, after the insidetemperature of the heat treatment furnace is decreased from thetemperature of T₈° C. to 700° C. at a rate of 3° C./min, the wafer canbe unloaded from the heat treatment furnace.

In order to sufficiently obtain the effect of the second aspect of themethod for manufacturing an annealed wafer according to the presentinvention, an oxygen concentration of a silicon wafer to be subjected toheat treatment is desirably set to about 14 ppma to 17 ppma. When theoxygen concentration is higher, a precipitate density becomes higher,and a more excellent IG capability can be obtained. However, when theoxygen concentration is excessively high, precipitates in the vicinityof the wafer surface are not easily annihilated. In addition, when theoxygen concentration is low, the density of grown-in precipitationnuclei formed in the step of growing a silicon single crystal is low,with the result that the precipitate density becomes low. Incidentally,even though the oxygen concentration is low, for example, thetemperature increase starting temperature T₆° C. of the temperatureincrease step A₁ is lowered, or the rate of R₃° C./min is lowered,whereby the effect of the second aspect of the method for manufacturingan annealed wafer according to the present invention can be obtained.

According to the second aspect of the method for manufacturing anannealed wafer of the present invention, an effect of suppressing thegeneration of slip dislocation due to thermal stress in devicefabrication processes. It is known that the dislocation constituting theslip is subjected to pinning by an oxide precipitate. Therefore,according to the second aspect of the method for manufacturing anannealed wafer of the present invention, when oxide precipitates eachhaving a large size are formed at a high density, the dislocation issubjected to pinning at a high probability, and the generation of theslip dislocation is suppressed. That is, the second aspect of the methodfor manufacturing an annealed wafer according to the present inventioncan be especially preferably applied to a large diameter wafer having adiameter of 300 mm or larger, in which the slip dislocation is easilygenerated by heat treatment.

In order to suppress the generation of the slip dislocation, thetemperature of T₈° C. is preferably set to 1200° C. or lower, and morepreferably about 1150° C. or lower.

In addition, according to the second aspect of the method formanufacturing an annealed wafer of the present invention, there can beformed a wafer with a high-quality DZ-IG structure where not only oxideprecipitates but also COP and voids are rarely present. From theviewpoint of suppressing the generation of the slip, this is especiallyadvantageous as to the 300 mm wafer that will be a mainstream in thefuture.

By performing the heat treatment on the wafer, a denuded zone (a voiddefect free and oxide precipitate free layer) having a sufficient depthcan be obtained, and at the same time, in not only an Nv region but alsoan Ni region where oxygen is not easily precipitated, oxide precipitateseach having a size detectable in the wafer bulk and not smaller than asize which achieves a gettering capability can be sufficiently obtainedwithout additionally performing special heat treatment after the aboveheat process (i.e., at the stage before loading the wafer into thedevice fabrication processes).

A silicon wafer to be used in the method for the present invention isobtained according to one of the silicon single crystal growing methodsdisclosed in JP A 2002-201093. That is, the silicon wafer is processedfrom a silicon single crystal obtained in such a way that, when a growthrate of pulling the silicon single crystal is gradually reduced in caseof growing the silicon single crystal by the Czochralski method, thegrowth rate is controlled to a growth rate between a first growth rateat a boundary where a defective region left after annihilation of an OSFring and detectable by the Cu deposition method is annihilated and asecond growth rate at a boundary where an interstitial dislocation loopis generated when the growth rate is further gradually reduced.

A wafer sliced from the single crystal rod grown by the above method isa non-defective silicon single crystal wafer which has a wafer entiresurface constituted by an N region outside an OSF in the form of a ringgenerated when performing a thermal oxidation process and which isperfectly free from a defective region detectable by the Cu depositionmethod.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart showing an example of an order of steps of afirst aspect of a method for manufacturing a silicon wafer according tothe present invention.

FIG. 2 is an explanatory view showing diagrammatically a main part ofthe order of steps in FIG. 1.

FIG. 3 is a flow chart showing an example of an order of steps of asecond aspect of the method for manufacturing a silicon wafer accordingto the present invention.

FIG. 4 is an explanatory view showing diagrammatically a main part ofthe order of steps in FIG. 3.

FIG. 5 is a schematic explanatory view showing an example of a singlecrystal pulling apparatus used in a single crystal pulling step in themethod of the present invention.

FIG. 6 is a schematic diagram for explaining another example of thesingle crystal pulling apparatus used in the single crystal pulling stepin the method of the present invention.

FIG. 7 is a graph showing a relationship between a depth from thesurface of an annealed wafer and a TZDB good chip yield in Example 1.

FIG. 8 is a graph showing a relationship between a depth from thesurface of an annealed wafer and a TZDB good chip yield in ComparativeExample 1.

FIG. 9 is an explanatory view showing an example of a relationshipbetween a single crystal growth rate and a crystal defect distribution.

FIG. 10 is an explanatory view showing another example of therelationship between a single crystal growth rate and a crystal defectdistribution.

BEST MODE FOR CARRYING OUT THE INVENTION

Description will be given of embodiments of the present invention belowbased on the accompanying drawings and examples shown in the figures arepresented by way of illustration, and it is needless to say that variousmodifications or alterations can be effected as far as not departingfrom the technical concept of the present invention.

An annealed wafer according to the present invention is an annealedwafer obtained by performing heat treatment on a silicon wafermanufactured from a silicon single crystal grown by the Czochralskimethod, wherein a good chip yield of an oxide film dielectric breakdowncharacteristic in a region having at least a depth of up to 5 μm from awafer surface is 95% or more, and a density of oxide precipitatesdetectable in the wafer bulk and each having a size not smaller than asize showing a gettering capability is not less than 1×10⁹/cm³.

As the silicon wafer, there is preferably used a silicon wafer which ismanufactured from a silicon single crystal grown under a condition that,when growing the silicon single crystal, a wafer entire surface is an Nregion which is formed outside an OSF generated in the form of a ring ina thermal oxidation process, and is free from a defective regiondetectable by a Cu deposition method. The silicon wafer can bemanufactured by a single crystal growth method used in the method forthe present invention (will be described later).

Also, as the silicon wafer, there may be used a less defective waferhaving almost no COP and voids (i.e., a wafer having an entire surfaceconstituted by an N region) which is manufactured from a silicon singlecrystal pulled under a condition that, when growing the silicon singlecrystal, void defects are suppressed. The less defective wafer, asdescribed in JP A 11-147786, JP A 11-157996 and the like, can beobtained by using a known technique for pulling a crystal whilecontrolling a ratio F/G of a crystal pulling rate F and a temperaturegradient G in the vicinity of a solid-liquid interface in the-crystal.

A method for manufacturing an annealed wafer according to the presentinvention will be described below. FIG. 1 is a flow chart showing anexample of an order of steps in a first aspect of the method formanufacturing an annealed wafer according to the present invention, andFIG. 2 is an explanatory view showing diagrammatically a main part ofthe order of steps in FIG. 1. As shown in FIG. 1, a wafer havinggrown-in precipitation nuclei to be subjected to heat treatment isprepared (step 200).

As the wafer, there is preferably used a wafer which has a wafer entiresurface constituted by an N region outside an OSF in the form of a ringgenerated when performing a thermal oxidation process and which is freefrom a defective region detectable by the Cu deposition method. Morespecifically, there may be used a silicon wafer processed from a siliconsingle crystal obtained in such a way that, when a growth rate ofpulling the silicon single crystal is gradually reduced in case ofgrowing the silicon single crystal by the Czochralski method, the growthrate is controlled to a growth rate between a first growth rate at aboundary where a defective region left after annihilation of an OSF ringand detectable by the Cu deposition method is annihilated and a secondgrowth rate at a boundary where an interstitial dislocation loop isgenerated when the growth rate is further gradually reduced.

An embodiment of a structure of an apparatus for pulling the siliconsingle crystal will be described below with reference to FIGS. 5 and 6.As shown in FIG. 5, the single crystal pulling apparatus 30 comprises apulling chamber 31, a crucible 32 arranged in the pulling chamber 31, aheater 34 arranged around the crucible 32, a crucible holding shaft 33and a rotating mechanism (not shown) which rotates the crucible 32, aseed chuck 6 for holding a seed crystal of silicon, a wire 7 for pullingthe seed chuck 6, and a winding mechanism (not shown) for rotating orwinding the wire 7. The crucible 32 includes an inner quartz cruciblecontaining a silicon melt 2, and an outer graphite crucible arrangedoutside the quartz crucible. A heat insulating material 35 is arrangedaround the heater 34.

In order to set a growth condition for the single crystal growth method,an annular graphite cylinder (heat shielding plate) 9 is arranged. InFIG. 6, an annular outside heat-insulating material 10 is arrangedaround a crystal solid-liquid interface 4. The annular outside heatinsulating material 10 is arranged with an interval of 2 to 20 cmbetween the lower end thereof and a surface 3 of the silicon melt 2. Inaddition, a cooling gas may be sprayed, or a cylindrical coolingapparatus that shields radiant heat to cool a single crystal may bearranged. Particularly, in recent years, there is frequently used aso-called MCZ method (described below) where a magnet (not shown) isarranged outside the pulling chamber 31 to apply a magnetic field to thesilicon melt 2 in a horizontal direction, a vertical direction, or thelike, so that the convection of the melt is suppressed to stably growthe single crystal. In FIGS. 5 and 6, reference numeral 4 denotes asolid-liquid interface indicating a boundary between a silicon singlecrystal and a silicon melt.

A single crystal growth method using the single crystal pullingapparatus 30 will be described below. First, a high-purity siliconpolycrystal material is heated to the melting point (about 1420° C.) orhigher to melt the material in the crucible 32. Next, the wire 7 isunwounded to bring the distal end of the seed crystal into contact withthe almost central portion of the surface of the silicon melt 2 or dipthe distal end in the silicon melt 2. Thereafter, the crucible holdingshaft 33 is rotated in a proper direction, and the wire 7 is wound whilebeing rotated to pull the seed crystal, so that single crystal growth isstarted. Subsequently, the pulling rate and temperature areappropriately controlled, so that an almost columnar single crystal rod1 can be obtained.

In this case, it is very important that, as shown in FIG. 5 or 6, anannular graphite cylinder (heat insulating plate) 9 and the annularoutside heat insulating material 10 are arranged such that a temperaturerange of from the melting point of the crystal in the vicinity of themelt surface to 1400° C. can be controlled in a peripheral space of theliquid portion in the single crystal rod 1 on the melt surface in thepulling chamber 31.

More specifically, in order to control the inside temperature of thefurnace, for example, as shown in FIG. 6, the annular outside heatinsulating member 10 may be arranged in the pulling chamber 31 such thatthe interval between the lower end thereof and the melt surface is setto the range of from 2 to 20 cm. In this manner, there becomes small thedifference between a temperature gradient Gc [° C./cm] of the centralportion of the crystal and a temperature gradient Ge of the peripheralportion of the crystal; for example, the inside temperature of thefurnace can be controlled such that the temperature gradient of theperipheral portion of the crystal is lower than that of the centralportion thereof. The annular outside heat insulating member 10 isarranged outside a graphite cylinder 12, and a heat insulating material11 is also arranged inside the graphite cylinder 12. The upper portionof the graphite cylinder 12 is connected to a metal cylinder 13, and acooling cylinder 14 is arranged on the metal cylinder 13, in which acoolant is flowed to forcibly cool the single crystal.

A silicon single crystal wafer obtained by slicing the silicon singlecrystal obtained as described above is a non-defective wafer which has awafer entire surface constituted by an N region outside an OSF in theform of a ring generated when performing a thermal oxidation process andwhich is free from a defective region detectable by the Cu depositionmethod. By using the wafer described above, there is preferable an oxidefilm dielectric breakdown characteristic of a surface layer of the wafersubjected to heat treatment.

In addition, it is preferable not to add nitrogen to the wafer in thecrystal growth step. In this manner, there is a poor chance of leavingoxide precipitates in the surface layer of the wafer subjected to heattreatment and doping of nitrogen is not necessary, so that the crystalproducing steps are not complicated and management thereof or the likebecomes easy.

The wafer manufactured by the above method is loaded into the heattreatment furnace (step 202). The heat treatment furnace is kept at atemperature of T₄° C. (500° C. to 700° C.). Before the next temperatureincrease step, the loaded wafer is kept at the temperature of T₄° C. fora predetermined time (time t₁), preferably, 15 minutes or longer (thepre-temperature-increase keeping step: step 204).

As well shown in FIG. 2, the inside temperature of the furnace isincreased from T₄° C. to T₅° C. set between the temperature of 1000° C.to 1230° C. at a temperature increase rate of R° C./min which is 5°C./min or lower (the temperature increase step: step 206). In thistemperature increase step (step 206), grown-in precipitation nuclei at ahigh density can be efficiently grown without being annihilated.

When it is desired to change the density of the oxide precipitatesdepending on the degree of contamination in device fabricationprocesses, for example, T₅° C. is set to about 1100° C., the temperatureincrease rate R° C./min is fixed to about 3° C./min, and T₄° C. ischanged, so that the density can be easily changed.

The wafer is kept at the temperature of T₅° C. for a predetermined time(time t₂) (the post-temperature-increase keeping step: step 208). Here,the keeping time is preferably set at about 30 minutes or longer. In thepost-temperature-increase keeping step (step 208), microscopic oxideprecipitates grown in a wafer bulk in the previous temperature increasestep (step 206) are grown to oxide precipitates each having a desiredsize of about 30 nm to 40 nm, preferably, about 50 nm or more indiameter, and at the same time, oxygen in the vicinity of the wafersurface is outdiffused to annihilate oxygen precipitation nuclei, sothat a DZ layer free from oxide precipitates can be formed.

Thus, the object of the post-temperature-increase keeping step (step208) at T₅° C. is to further grow oxide precipitates grown in the waferbulk in the temperature increase step (step 206) and to outdiffuseoxygen in the vicinity of the wafer surface. Therefore, if the objectcan be achieved, this step is not limited to the step of keeping thewafer at a constant temperature, and it can be changed into a step witha slight change in temperature (temperature increase, temperaturedecrease, or the like). In addition, by changing T₅° C. and the keepingtime t₂ in the post-temperature-increase keeping step (step 208), thesize of oxide precipitates can be easily changed.

After the heat treatment, for example, the temperature in the heattreatment furnace is decreased from T₅° C. to 700° C. at a rate of 2°C./min (the temperature decrease step: step 210), the wafer is unloadedfrom the heat treatment furnace (step 212). Incidentally, thetemperature decrease rate and the ultimate temperature after thetemperature decrease are not limited to specific values.

An atmosphere for the heat treatment is not limited. For example, anoxygen atmosphere, an oxygen-nitrogen mixture atmosphere, an argonatmosphere, and a hydrogen atmosphere, and the like are usable. In anon-oxidation atmosphere such as argon or hydrogen, an oxide film is notformed on a wafer surface, with the result that outdiffusion of oxygenin the non-oxidation atmosphere may be preferably accelerated more thanthat in an oxidation atmosphere.

In order to sufficiently obtain the effect of the heat treatment methodof the present invention, the oxygen concentration of the silicon waferto be subjected to heat treatment is desirably set to about 14 to 17ppma. When the oxygen concentration is higher, a precipitate densitybecomes higher, and a more excellent IG capability can be given. Whenthe oxygen concentration is higher, a growth rate of the precipitatesbecomes higher, with the result that a total process time is shortened.

FIG. 3 is a flow chart showing an example of an order of steps of asecond aspect of the method for manufacturing a silicon wafer accordingto the present invention, and FIG. 4 is an explanatory view showingdiagrammatically a main part of the order of steps in FIG. 3. As shownin FIGS. 3 and 4, the second aspect of the method for manufacturing anannealed wafer according to the present invention includes, as necessarysteps, a temperature increase step A₁ (step 304) for growing grown-inprecipitation nuclei formed in the a silicon single crystal growingstep, a temperature increase step B₁ (step 306) for efficientlyincreasing a temperature to a higher keeping temperature, and aconstant-temperature keeping step C₁ (step 308) for growing the grown-inprecipitation nuclei to oxide precipitates each having a size notsmaller than a size having a gettering capability and for outdiffusingoxygen in the vicinity of the silicon wafer surface. Incidentally, inFIGS. 3 and 4, as a preferable example, there is shown a case in whichthe temperature increase step A₁ (step 304), the temperature increasestep B₁ (step 306), and the constant-temperature keeping step C₁ (step308) are continuously performed.

As shown in FIG. 3, there is prepared a wafer to be subjected to heattreatment and having grown-in precipitation nuclei (step 300). As thewafer, a silicon wafer used in the first aspect of the method formanufacturing an annealed wafer according to the present invention issimilarly used. The wafer is loaded into a heat treatment furnace keptat a temperature of T₆° C. (step 302). Here, T₆° C. is preferably set to700° C. or lower.

Next, as well shown in FIG. 4, an inside temperature of the furnace isincreased from T₆° C. to T₇° C. at a rate of R₃° C./min (the temperatureincrease step A₁: step 304). Here, T₇° C. is preferably set to the rangeof 800° C. to 1000° C., and the rate of R₃° C./min is preferably set to3° C./min or lower. Also, before increasing a temperature from T₆° C. toT₇° C. in the temperature increase step A₁ (step 304), the keeping timet₃ at T₆° C. may be 0, but preferably 30 minutes or longer. In thistemperature increase step A₁ (step 304), high density grown-inprecipitation nuclei can be efficiently grown without being annihilated.

Next, the inside temperature of the heat treatment furnace is increasedfrom T₇° C. to T₈° C. at a rate of R₄° C. (the temperature increase stepB₁: step 306). Here, T₈° C. is preferably set to the range of 1050° C.to 1230° C., and the rate of R₄° C. is preferably set to 5° C./min orhigher. In this temperature increase step B₁ (step 306), the insidetemperature of the furnace is increased to a higher keeping temperaturewithin a short time to make it possible to easily annihilateprecipitates in the vicinity of the wafer surface without growingunnecessary precipitates.

Further, T₈° C. is kept for a keep time t₄ (the constant-temperaturekeeping step C₁: step 308). Here, T₈° C. is preferably set to the rangeof 1050° C. to 1230° C., and the keeping time t₄ is preferably set toabout 30 minutes or longer. In this constant-temperature keeping step C₁(step 308), microscopic oxide precipitates grown in the wafer bulk inthe previous temperature increase steps (steps 304 and 306) are grown tooxide precipitates each having a desired size of about 40 nm or larger,more preferably, about 50 nm or larger in diameter, and at the same timeoxygen in the vicinity of the wafer surface is outdiffused to annihilatethe oxide precipitates, so that a DZ layer free from oxide precipitatescan be formed.

In this case, since the oxide precipitates in the vicinity of the wafersurface can be more perfectly annihilated, a DZ layer of very highquality can be efficiently obtained.

The object of the constant-temperature keeping step C₁ (step 308) at T₈°C. is to further grow oxide precipitates grown in the wafer bulk in thetemperature increase step (steps 304 and 306) and to outdiffuse oxygenin the vicinity of the wafer surface. Therefore, if the object can beachieved, the step is not limited to the step of keeping the wafer at aconstant temperature, and can be changed into a step with a slightchange in temperature (temperature increase, temperature decrease, orthe like). In addition, when T₈° C. and the keeping time t₄ in theconstant-temperature keeping step C₁ (step 308) are changed, the size ofoxide precipitates and a DZ width can be easily changed.

After the heat treatment, for example, after the inside temperature ofthe heat treatment furnace is decreased from T₈ to 700° C. at a rate of3° C./min (the temperature decrease step: step 310), the wafer isunloaded from the heat treatment furnace (step 312). Incidentally, thetemperature decrease rate and the ultimate temperature after thetemperature decrease are not limited to specific values.

An atmosphere for the heat treatment is not limited. For example, anoxygen atmosphere, an oxygen-nitrogen mixture atmosphere, an argonatmosphere, and a hydrogen atmosphere, and the like are usable. In anon-oxidation atmosphere such as argon or hydrogen, an oxide film is notformed on a wafer surface; with the result that outdiffusion of oxygenin the non-oxidation atmosphere may be preferably accelerated more thanthat in an oxidation atmosphere.

In order to sufficiently obtain the effect of the second aspect of themethod for manufacturing an annealed wafer according to the presentinvention, the oxygen concentration of the silicon wafer to be subjectedto heat treatment is desirably set to the range on the order of 14 ppmato 17 ppma. When the oxygen concentration is higher, a density ofprecipitates becomes higher, and a more excellent IG capability can begiven. However, when the oxygen concentration is excessively high,precipitates in the vicinity of the wafer surface are not easilyannihilated. When the oxygen concentration decreases, a density ofgrown-in precipitation nuclei formed in the step of growing a siliconsingle crystal becomes low, and a density of precipitates becomes low.Incidentally, even though the oxygen concentration is low, by decreasingthe temperature increase start temperature T₆° C. of the temperatureincrease step A₁, or by decreasing the rate of R₃° C./min, the effect ofthe second aspect of the method for manufacturing an annealed waferaccording to the present invention can be obtained.

EXAMPLES

The present invention will be described below in more specific manner byway of the following examples which should be construed as illustrativerather than restrictive.

Example 1

A silicon single crystal was pulled by the Czochralski method in aregion of (Nv−Dn)+Ni in FIG. 10 (JP A 2002-201093) under controlling agrowth rate between a first growth rate at a boundary where a defectiveregion (Dn) left after annihilation of an OSF ring and detectable by aCu deposition method is annihilated when the growth rate of pulling asilicon single crystal was gradually reduced, and a second rate at aboundary (a boundary between an N region and an I region) where aninterstitial dislocation loop is generated when the growth rate isfurther gradually reduced, so that there was prepared a mirror-polishedsilicon wafer manufactured from a silicon single crystal pulled in acondition that the generation of voids was suppressed.

In the growth of the crystal, nitrogen was not added. The wafer has adiameter of 8 inches, a crystal orientation of <100>, and a resistivityof about 10 Ω·cm (boron doped). Wafers of two types having differentoxygen concentrations were prepared. The oxygen concentrations are about15 and 17 ppma (JEIDA scale), respectively. JEIDA is the abbreviatedname of Japan Electronic Industry Development Association (at present,JEIDA is changed into JEITA: Japan Electronics and InformationTechnology industries Association). The wafers were evaluated by the Cudeposition method, with the result that no defects were detected.

Then, the wafers were subjected to heat treatment in an argonatmosphere. More specifically, the wafers were loaded into a heattreatment furnace at a temperature of 700° C. and kept for 30 minutes.Thereafter, the temperature was increased to 900° C. at a rate of 3°C./min, increased to 1150° C. at a rate of 5° C./min, and the waferswere kept at 1150° C. for 4 hours. After the keeping, the insidetemperature of the heat treatment furnace was decreased to 700° C. at arate of 3° C./min, and the wafers were unloaded from the heat treatmentfurnace.

On each of the wafers (annealed wafers) subjected to the heat treatment,a polishing process was performed by mechanical-chemical polishing in adepth of the order of 3 to 13 μm from the wafer surface, and oxide filmdielectric breakdown characteristics [TZDB (Time Zero DielectricBreakdown) good chip yields] at respective depths were measured. In themeasurement of the TZDB good chip yield, thermal oxide films each havinga thickness of about 25 nm were formed on the wafer surfaces, andphosphorous-doped polysilicon electrodes (electrode area: 8 mm²) weremanufactured on the respective thermal oxide films. The determinationcurrent value was set to 1 mA/cm², and a wafer having a dielectricbreakdown electric field of 8 MV/cm or more was determined as a goodchip. Measurement was performed at 100 points on the surface of eachwafer, and good chip yields were calculated. The results are shown inFIG. 7.

As is apparent from FIG. 7, in all cases of the oxygen concentrations,the good chip yields in the regions having a depth of at least up to 5μm were almost 100%, and those in the regions having a depth of up to onthe order of 6 to 7 μm were 95% or more.

Furthermore, on the wafers subjected to the heat treatment, a density ofthe oxide precipitates in each of the wafer bulks was measured byinfrared scattering tomography without addition of further heattreatment. According to the infrared scattering tomography, oxideprecipitates each having a size with a diameter of 40 nm or more can bedetected. As a result, when the oxygen concentration was about 15 ppma,the density of oxide precipitates was about 5×10⁹/cm³, and when theoxygen concentration was about 17 ppma, the density was about 9×10⁹/cm³.Therefore, it was found that oxide precipitates having a high densitywere detected without device fabrication processes.

Example 2

The silicon mirror-polished wafers manufactured in the same conditionsas those in Example 1 were subjected to the following heat treatment inan argon atmosphere. That is, the wafers were kept at 700° C. for 1hour, the temperature was increased to 900° C. at a rate of 3° C./min,and increased from 900° C. to 1200° C. at a rate of 5° C./min, and thewafers were kept at 1200° C. for 1 hour. After the keeping, the insidetemperature of the heat treatment furnace was decreased to 700° C. at arate of 3° C./min, and the wafers were unloaded from the heat treatmentfurnace.

On the wafers (annealed wafers) subjected to the heat treatment, TZDBgood chip yields and densities of the oxide precipitates were measuredunder the same conditions as those in Example 1. As a result, in allcases of the oxygen concentrations, as in Example 1, the good chipyields in the regions having a depth of at least up to 5 μm were almost100%, and those in the regions having a depth of up to on the order of 6to 7 μm were 95% or more. With respect to densities of the oxideprecipitates, when the oxygen concentration was about 15 ppma, thedensity of oxide precipitates was about 4×10⁹/cm³, and when the oxygenconcentration was about 17 ppma, the density was about 8×10⁹/cm³.Therefore, it was found that oxide precipitates having a high densitywere detected without device fabrication processes.

Comparative Example 1

There was prepared a mirror-polished silicon wafer manufactured from asilicon single crystal pulled at pulling rate slightly faster than thatin Example 1. In the growth of the crystal, nitrogen was not added. Thewafer has a diameter of 8 inches, a crystal orientation of <100>, and aresistivity of about 10 Ω·cm (boron doped). The oxygen concentration ofthe wafer was about 15 ppma. When the wafer was evaluated by the Cudeposition method, defects were detected.

Next, the wafer was subjected to the heat treatment under the sameconditions as those in Example 1. A TZDB good chip yield is shown inFIG. 8. From the result, it is found that good chip yields in the regionhaving a depth of up to about 6 μm were about 90% or more at a highlevel, but in comparison with the result in Example 1 (FIG. 7), thewafer in Comparative Example 1 is inferior to that in Example 1. Thedensity of the oxide precipitates in the wafer bulk was about 5×10⁹/cm³,which was the same level as that in Example 1.

As described above, when there is subjected to heat treatment a siliconwafer in which a defective region detected by the Cu deposition methodis not present, the good chip yield of the oxide film dielectricbreakdown characteristic in the region having a depth of at least up to5 μm from the wafer surface is 95% or more, and a density of defectsdetectable in the wafer bulk is 1×10⁹/cm³ or more at the stage beforethe wafer is loaded into device fabrication processes. That is, therecan be obtained an annealed wafer including a wafer surface layer havingan excellent oxide film dielectric breakdown characteristic and a waferbulk layer having an excellent gettering capability.

CAPABILITY OF EXPLOITATION IN INDUSTRY

As described above, according to the present invention, there can beprovided an annealed wafer which has a wafer surface layer serving as adevice fabricating region and having an excellent oxide film dielectricbreakdown characteristic, and a wafer bulk layer in which oxideprecipitates are present at a high density at the stage before the waferis loaded into the device fabrication processes to give an excellent IGcapability, and a method for manufacturing the annealed wafer.

1. An annealed wafer obtained by performing heat treatment on a siliconwafer manufactured from a silicon single crystal grown by theCzochralski method, wherein a good chip yield of an oxide filmdielectric breakdown characteristic in a region having at least a depthof up to 5 μm from a wafer surface is 95% or more, and a density ofoxide precipitates detectable in the wafer bulk and each having a sizenot smaller than a size showing a gettering capability is not less than1×10⁹/cm³.
 2. The annealed wafer according to claim 1, wherein thesilicon wafer is manufactured from a silicon single crystal grown undera condition that, when growing the silicon single crystal, a waferentire surface is an N region which is formed outside an OSF generatedin the form of a ring in a thermal oxidation process, and is free from adefective region detectable by a Cu deposition method.
 3. The annealedwafer according to claim 2, wherein the silicon wafer is manufacturedfrom a silicon single crystal grown without adding nitrogen when growingthe silicon single crystal.
 4. The annealed wafer according to claim 1,wherein the silicon wafer is manufactured from a silicon single crystalgrown without adding nitrogen when growing the silicon single crystal.5. A method for manufacturing an annealed wafer comprising the steps of:manufacturing a silicon wafer from a silicon single crystal obtained bygrowing the silicon single crystal under controlling a growth ratebetween a first growth rate at a boundary where a defective region leftafter annihilation of an OSF ring and detectable by a Cu depositionmethod is annihilated when the growth rate of pulling a silicon singlecrystal is gradually reduced, and a second growth rate at a boundarywhere an interstitial dislocation loop is generated when the growth rateis further gradually reduced in case of growing the silicon singlecrystal by a Czochralski method; keeping the silicon wafer havinggrown-in precipitation nuclei formed in the step of growing the siliconsingle crystal at a temperature of T₄° C. in the range of 500° C. to700° C. for a predetermined time t₁; increasing the temperature of thesilicon wafer to a temperature of T₅° C. in the range of 1000° C. to1230° C. with a temperature increase rate of 5° C./min or less; andkeeping the silicon wafer at the temperature of T₅° C. for apredetermined time t₂, whereby the grown-in precipitation nuclei aregrown to oxide precipitates each having a size not smaller than a sizehaving a gettering capability and oxygen in the vicinity of the siliconwafer surface is outdiffused.
 6. The method for manufacturing anannealed wafer according to claim 5, wherein the keeping time t₁ at thetemperature of T₄° C. is 15 minutes or more.
 7. The method formanufacturing an annealed wafer according to claim 6, wherein thekeeping time t₂ at the temperature of T₅° C. is 30 minutes or more. 8.The method for manufacturing an annealed wafer according to claim 5,wherein the keeping time t₂ at the temperature of T₅° C. is 30 minutesor more.
 9. A method for manufacturing an annealed wafer comprising thesteps of: manufacturing a silicon wafer from a silicon single crystalobtained by growing the silicon single crystal under controlling agrowth rate between a first growth rate at a boundary where a defectiveregion left after annihilation of an OSF ring and detectable by a Cudeposition method is annihilated when the growth rate of pulling asilicon single crystal is gradually reduced, and a second growth rate ata boundary where an interstitial dislocation loop is generated when thegrowth rate is further gradually reduced in case of growing the siliconsingle crystal by a Czochralski method; and heat treating the siliconwafer having grown-in precipitation nuclei formed in the step of growingthe silicon single crystal to give a getting capability to the siliconwafer, wherein there are performed at least three steps including atemperature increase step A₁ for growing the grown-in precipitationnuclei, a temperature increase step B₁ for increasing a temperature to ahigher keeping temperature, and a constant-temperature keeping step C₁for growing the grown-in precipitation nuclei to oxide precipitates eachhaving a size not smaller than a size having a gettering capability andfor outdiffusing oxygen in the vicinity of the silicon wafer surface.10. The method for manufacturing an annealed wafer according to claim 9,wherein the temperature increase step A₁, the temperature increase stepB₁, and the constant-temperature keeping step C₁ are continuouslyperformed.
 11. The method for manufacturing an annealed wafer accordingto claim 10, wherein the temperature increase step A₁ is for increasinga temperature from T₆° C. to T₇° C. at a rate of R₃° C./min, T₆° C. is700° C. or less, T₇° C. is in the range of 800° C. to 1000° C., and R₃°C./min is 3° C./min or less.
 12. The method for manufacturing anannealed wafer according to claim 11, wherein before increasing thetemperature from T₆° C. to T₇° C. in the temperature increase step A₁,the temperature of T₆° C. is kept for 30 minutes or more.
 13. The methodfor manufacturing an annealed wafer according to claim 12, wherein thetemperature increase step B₁ is for increasing the temperature from T₇°C. to T₈ C at a rate of R₄° C./min, T₇° C. is in the range of 800° C. to1000° C., T₈° C. is in the range of 1050° C. to 1230° C., and R₄° C./minis 5° C./min or more.
 14. The method for manufacturing an annealed waferaccording to claim 11, wherein the temperature increase step B₁ is forincreasing the temperature from T₇° C. to T₈ C at a rate of R₄° C./min,T₇° C. is in the range of 800° C. to 1000° C., T₈° C. is in the range of10500° to 1230° C., and R₄° C./min is 5° C./min or more.
 15. The methodfor manufacturing an annealed wafer according to claim 10, whereinbefore increasing the temperature from T₆° C. to T₇° C. in thetemperature increase step A₁, the temperature of T₆° C. is kept for 30minutes or more.
 16. The method for manufacturing an annealed waferaccording to claim 15, wherein the temperature increase step B₁ is forincreasing the temperature from T₇° C. to T₈ C at a rate of R₄° C./min,T₇° C. is in the range of 800° C. to 1000° C., T₈° C. is in the range of1050° C. to 1230° C., and R₄° C./min is 5° C./min or more.
 17. Themethod for manufacturing an annealed wafer according to claim 10,wherein the temperature increase step B₁ is for increasing thetemperature from T₇° C. to T₈ C at a rate of R₄° C./min, T₇° C. is inthe range of 800° C. to 1000° C., T₈° C. is in the range of 10500° to1230° C., and R₄° C./min is 5° C./min or more.
 18. The method formanufacturing an annealed wafer according to claim 9, wherein thetemperature increase step A₁ is for increasing a temperature from T₆° C.to T₇° C. at a rate of R₃° C./min, T₆° C. is 700° C. or less, T₇° C. isin the range of 800° C. to 1000° C., and R₃° C./min is 3° C./min orless.
 19. The method for manufacturing an annealed wafer according toclaim 18, wherein before increasing the temperature from T₆° C. to T₇°C. in the temperature increase step A₁, the temperature of T₆° C. iskept for 30 minutes or more.
 20. The method for manufacturing anannealed wafer according to claim 19, wherein the temperature increasestep B₁ is for increasing the temperature from T₇° C. to T₈ C at a rateof R₄° C./min, T₇° C. is in the range of 800° C. to 1000° C., T₈° C. isin the range of 1050° C. to 1230° C., and R₄° C./min is 5° C./min ormore.
 21. The method for manufacturing an annealed wafer according toclaim 18, wherein the temperature increase step B₁ is for increasing thetemperature from T₇° C. to T₈ C at a rate of R₄° C./min, T₇° C. is inthe range of 800° C. to 1000° C., T₈° C. is in the range of 10500° to1230° C., and R₄° C./min is 5° C./min or more.
 22. The method formanufacturing an annealed wafer according to claim 9, wherein beforeincreasing the temperature from T₆° C. to T₇° C. in the temperatureincrease step A₁, the temperature of T₆° C. is kept for 30 minutes ormore.
 23. The method for manufacturing an annealed wafer according toclaim 22, wherein the temperature increase step B₁ is for increasing thetemperature from T₇° C. to T₈ C at a rate of R₄° C./min, T₇° C. is inthe range of 800° C. to 1000° C., T₈° C. is in the range of 1050° C. to1230° C., and R₄° C./min is 5° C./min or more.
 24. The method formanufacturing an annealed wafer according to claim 9, wherein thetemperature increase step B₁ is for increasing the temperature from T₇°C. to T₈ C at a rate of R₄° C./min, T₇° C. is in the range of 800° C. to1000° C., T₈° C. is in the range of 1050° C. to 1230° C., and R₄° C./minis 5° C./min or more.